LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

ENTITY ic_9 IS

    PORT(clear, pin1, pin2, pin11, pin12, pin13, pin14, pin7, pin9, pin10, pin15: IN STD_LOGIC := '0'; 
        pin3, pin4, pin5, pin6: OUT STD_LOGIC := '0');

END ic_9;

ARCHITECTURE bit4_register_ic OF ic_9 IS

SIGNAL REG: STD_LOGIC_VECTOR(4 DOWNTO 1) := "0000";

BEGIN

    pin3 <= REG(1);
    pin4 <= REG(2);
    pin5 <= REG(3);
    pin6 <= REG(4);

    PROCESS(pin1, pin2, pin11, pin12, pin13, pin14, pin7, pin9, pin10)
    BEGIN
        IF(pin1 = '1' OR pin2 = '1') THEN --THE CI WILL BE IN HIGH-IMPEDANCE, SO THE PIN WILL BE AT GROUND OF PULL-DOWN RESISTOR
            REG <= "0000";
        ELSIF(pin15 = '1' OR clear = '1') THEN
            REG <= "0000";
        ELSE
            IF(pin7 = '1' AND pin7'EVENT) THEN
                IF(pin9 = '0' AND pin10 = '0') THEN
                    REG(1) <= pin14;
                    REG(2) <= pin13;
                    REG(3) <= pin12;
                    REG(4) <= pin11;
                ELSE
                    REG <= REG;
                END IF;
            END IF;
        END IF;
    END PROCESS;

END bit4_register_ic;